Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...
EDN

New generation of physical RTL synthesis improves QoR

The quality of the netlist generated during RTL synthesis has an enormous impact on the rest of the physical design flow. For teams designing large SoCs at advanced nodes, it is more important than ...
Business Insider

Mentor Graphics Expands Formal Verification's Reach with New Cross-Platform GUI and Apps for Sequential Logic Equivalence Checking and CDC Gate-Level Analysis

WILSONVILLE, Ore., April 20, 2017 /PRNewswire/ -- Mentor, a Siemens business, today announced new formal-based technologies in the Questa Verification Solution that provide RTL designers and ...
PC Magazine

soft core

A block of digital logic that is designed to be implemented in an ASIC or FPGA chip. A soft core is typically delivered in RTL, which is a hardware description language that defines logic at a higher ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...