IEEE

Improved Fractional $\mathrm{P}{\mathrm{I}}^{{\alpha }}{\mathrm{D}}^{{\beta }}$ Controller for AVR System via a New Optimization Algorithm

Abstract: In this study, a pioneering metaheuristic optimization approach, named Proportional-Integral-Derivative (PID)-based Search Algorithm (PSA), is suggested for the first time in the context of ...
IEEE

28 M Weights $\times$ TOPs $/ \mathrm{W}/\text{mm}^{2}$ PCM-Based Analog in-Memory Computing Core with 8 $512 \times 512{}$-Weight Layers in 28 nm FD-SOI CMOS

In-Memory Computing (IMC) hardware accelerators for Deep Neural Networks (DNNs) require massive quantity of coefficients stored in a single device to limit performance losses in multicore clusters.